QSSC -310FA Spezifikationen

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Inhaltsverzeichnis

Seite 1

QSSC-S4R Technical Product Specification Contents i QSSC-S4R Technical Product Specification Revision 1.0 September 14, 2010

Seite 2

x24.5.2 System Clock Synchronization ...

Seite 3 - Contents

Cables and Connectors QSSC-S4R Technical Product Specification 10011.2 Cable and Interconnect Descriptions The following table describes all cables

Seite 4

QSSC-S4R Technical Product Specification Cables and Connectors 101 Type Quantity From To Interconnect Description SATA 5 Main Board H

Seite 5

Cables and Connectors QSSC-S4R Technical Product Specification 102 Figure 49. COM Serial Port Connector 11.3.2 Video Ports The main board and front

Seite 6

QSSC-S4R Technical Product Specification Cables and Connectors 103 Table 42. Dual USB Connector Pin-out (Rear) Pin Signal Description 1 Fused

Seite 7

850W Power Supply QSSC-S4R Technical Product Specification 10412. 850W Power Supply This section describes some of the QSSC-S4R Power Supply featur

Seite 8

QSSC-S4R Technical Product Specification 850W Power Supply 105 A3 12VIBUS B6 PSALERT A4 ILOCAL B7 PSON A5 SCL B8 +15VCC A6 SDA B9 PSKILL A7 A0 B10 +

Seite 9

850W Power Supply QSSC-S4R Technical Product Specification 10612.3.6 Power Factor Correction (PFC) The power supply incorporates a Power Factor Cor

Seite 10

QSSC-S4R Technical Product Specification 850W Power Supply 107 12.4.4 Short Circuit Protection A short circuit, which is defined as an impedance of

Seite 11

850W Power Supply QSSC-S4R Technical Product Specification 10812.4.10 Power Supply Module LED indicators Figure 53. Power Supply Indicators Tabl

Seite 12

QSSC-S4R Technical Product Specification Power Distribution Board (PDB) 109 13. Power Distribution Board (PDB) This section describes the Quanta®

Seite 13 - List of Figures

QSSC-S4R Technical Product Specification Contents xi 24.32.1 Backplane Types ...

Seite 14

Power Distribution Board (PDB) QSSC-S4R Technical Product Specification 110 Figure 55. Power Supply Numbering on the PDB The QSSC-S4R PDB supports

Seite 15

QSSC-S4R Technical Product Specification Power Distribution Board (PDB) 111 Figure 56. PDB Functional Block Diagram 13.2.1 Connector Signal Descri

Seite 16 - List of Tables

Power Distribution Board (PDB) QSSC-S4R Technical Product Specification 112 Table 54. PDB Inlet Card Edge Interface – Component Side Pin Signal D

Seite 17

QSSC-S4R Technical Product Specification Power Distribution Board (PDB) 113 4 P12V 12 GND 5 P12V 13 GND 6 P12V 14 GND 7 P12V 15 GND 8 P12V 16

Seite 18

Power Distribution Board (PDB) QSSC-S4R Technical Product Specification 1147 SMB_LINK_3V3SB_CLK 8 GND 9 SMB_LINK_3V3SB_DAT 10 GND 11 PS1_PWRGOOD

Seite 19

QSSC-S4R Technical Product Specification Power Distribution Board (PDB) 115 *Provided by droop share and the loading only under static not apply to

Seite 20

Power Distribution Board (PDB) QSSC-S4R Technical Product Specification 116 1. PSAlert#_1 2. PSAlert#_2 3. PSAlert#_3 4. PSAlert#_4 5. PS1_OCP 6. P

Seite 21 - 1. Introduction

QSSC-S4R Technical Product Specification Power Distribution Board (PDB) 117 13.3.2 Cold Redundancy Functional Description The circuit always enable

Seite 22

Power Distribution Board (PDB) QSSC-S4R Technical Product Specification 118Figure 58. Power Sub-system Efficiency in Cold Redundant Operation The

Seite 23 - 2. Main Board

QSSC-S4R Technical Product Specification Front Panel Fan Board (FPFB) and Operator Panel 119 14. Front Panel Fan Board (FPFB) and Operator Panel T

Seite 24

xii29.1 Sensor Type Codes ...

Seite 25

Front Panel Fan Board (FPFB) and Operator Panel QSSC-S4R Technical Product Specification 12014.2 Front Panel Fan Board (FPFB) Functional Architectu

Seite 26

QSSC-S4R Technical Product Specification Front Panel Fan Board (FPFB) and Operator Panel 121 Table 67. System Fan Mapping System Fan PWM Tach F

Seite 27 - 2.2 Functional Architecture

Front Panel Fan Board (FPFB) and Operator Panel QSSC-S4R Technical Product Specification 1221 SMB_IPMB_3V3SB_CLK 2 GND 3 SMB_IPMB_3V3SB_DAT

Seite 28

QSSC-S4R Technical Product Specification Front Panel Fan Board (FPFB) and Operator Panel 123 3 LED_ID_P 9 LED_STBY_P 4 SW_NMI_N 10 LED

Seite 29

Front Panel Fan Board (FPFB) and Operator Panel QSSC-S4R Technical Product Specification 124 Figure 60. Operator Panel Controls and Indicators Tabl

Seite 30 - 2.2.2 Intel® 7500 Chipset

QSSC-S4R Technical Product Specification Front Panel Fan Board (FPFB) and Operator Panel 125 G System reset button Resets the system I System ID b

Seite 31 - 2.2.2.2 Intel® QPI Features

Basic Input/Output System (BIOS) QSSC-S4R Technical Product Specification 12615. Basic Input/Output System (BIOS) 15.1 BIOS Architecture The BIOS i

Seite 32 - 2.2.2.5 Controller Link (CL)

QSSC-S4R Technical Product Specification BIOS Initialization 127 16. BIOS Initialization 16.1 Processors QSSC-S4R server boards are four socket boar

Seite 33 - 2.3.1 ICH10R Southbridge

BIOS Initialization QSSC-S4R Technical Product Specification 128Table 79. CPU Population Rules for QSSC-S4R Number of CPUs CPU1 CPU2 CPU3 CPU41

Seite 34

QSSC-S4R Technical Product Specification BIOS Initialization 129 code. The system cannot boot unless the error is resolved. The user needs to replac

Seite 35

QSSC-S4R Technical Product Specification List of Figures xiii List of Figures Figure 1 Main Board Block Diagram ...

Seite 36 - 2.3.2 PCI-Express Subsystem

BIOS Initialization QSSC-S4R Technical Product Specification 130Error Severity System Action Population Rule Violation x Logs the error in the SE

Seite 37 - 2.3.6 Clock Subsystem

QSSC-S4R Technical Product Specification BIOS Initialization 131 16.1.15 Enhanced Halt State (C1E) All processors support the Halt State (C1) throug

Seite 38

BIOS Initialization QSSC-S4R Technical Product Specification 132x Turbo Boost operates under OS control – it is only entered when the OS requests

Seite 39 - 2.3.6.1.1 CK MNG

QSSC-S4R Technical Product Specification BIOS Initialization 133 Bit[7:0] 0x80 "LLC Array Error" 0x81 "Tag Array Error" 0x82

Seite 40 - 2.3.9 USB 2.0 Subsystem

BIOS Initialization QSSC-S4R Technical Product Specification 134The BIOS configures the memory system dynamically in accordance with the available

Seite 41 - 2.3.10 Post Code LEDs

QSSC-S4R Technical Product Specification BIOS Initialization 135 Any of the above errors also signal a memory error beep code. Memory beep code erro

Seite 42

BIOS Initialization QSSC-S4R Technical Product Specification 13616.2.4.1 Processor Cores, QPI Links and DDR3 Channels Frequency Configuration The

Seite 43

QSSC-S4R Technical Product Specification BIOS Initialization 137 Figure 62. QSSC-S4R System Memory Topology Figure 63. QSSC-S4R Memory DIMM Topol

Seite 44

BIOS Initialization QSSC-S4R Technical Product Specification 138x The optimization techniques like lock step are used by the Intel® Xeon® 7500 pro

Seite 45

QSSC-S4R Technical Product Specification BIOS Initialization 139 27. If NUMA is enabled, BIOS can have only 2-way interleaving enabled or NO interl

Seite 46

xivFigure 38. Fan Location ...

Seite 47 - 3.1 Introduction

BIOS Initialization QSSC-S4R Technical Product Specification 140 Figure 65. Population with Non-identical DDR3 DIMMs x DIMMs within a Lock step pa

Seite 48 - 3.1.2 Non IPMI Features

QSSC-S4R Technical Product Specification BIOS Initialization 141 Figure 67. Minimal Optimal Population Upgrade for RAS Modes x DIMM pairs {DIMM 1/

Seite 49 - 3.2 Functional Architecture

BIOS Initialization QSSC-S4R Technical Product Specification 142Table 82. Standard QSSC-S4R 4S Server Platforms DIMM Population Rules Memory Board

Seite 50 - 3.2.2 SMBus Block Diagram

QSSC-S4R Technical Product Specification BIOS Initialization 143 16.2.10.1 Lock Step Mode. Lock step mode is where cache lines are divided across lo

Seite 51

BIOS Initialization QSSC-S4R Technical Product Specification 144x Memory hot-plug can be supported in 2-way, 4-way or 8-way interleave mode but ho

Seite 52 - 3.3 Supported Features

QSSC-S4R Technical Product Specification BIOS Initialization 145 Figure 70. Intra-Socket Mirroring 16.2.10.4.2 Inter-Socket Mirroring Intel® Xeon®

Seite 53 - 3.3.5 Chassis Intrusion

BIOS Initialization QSSC-S4R Technical Product Specification 146Note: The arrow points from Primary to Secondary Copy of Memory DataCPU1CPU1MEM3_SL

Seite 54 - 4. Memory Riser

QSSC-S4R Technical Product Specification BIOS Initialization 147 Figure 72. Hemisphere Example 16.2.10.5.1 NUMA in Hemisphere Mode Hemisphere mode

Seite 55 - ® SMI Status Frame

BIOS Initialization QSSC-S4R Technical Product Specification 148Note: The arrow points from Primary to Secondary Copy of Memory DataCPU1CPU1MEM3_SL

Seite 56 - 4.2.2 DDR3 Functionality

QSSC-S4R Technical Product Specification BIOS Initialization 149 16.2.11.1 Detailed Flow The following flow illustrates the overall process of memor

Seite 57 - 4.3 Functional Architecture

QSSC-S4R Technical Product Specification List of Figures xv Figure 84. Setup Utility — Mass Storage Controller Configuration Screen ...

Seite 58 - 4.3.4 Power Rails

BIOS Initialization QSSC-S4R Technical Product Specification 150The following flow illustrates the overall process of hot-removal of memory board o

Seite 59 - 5. I/O Riser

QSSC-S4R Technical Product Specification BIOS Initialization 151 NUMA has to be enabled for any memory hot plug operations. Population rules for Mem

Seite 60 - 5.3 Video Subsystem

BIOS Initialization QSSC-S4R Technical Product Specification 15216.2.11.3.10 Memory Hot Replace in Inter Socket Mirroring Mode Memory Hot Replace

Seite 61 - 5.4 USB Subsystem

QSSC-S4R Technical Product Specification BIOS Initialization 153 16.2.12.1.3 Faulty Data Paths DDR-3 DIMM technology includes data paths from the DI

Seite 62

BIOS Initialization QSSC-S4R Technical Product Specification 154BIOS Error Manager Screen The BIOS reports RAS configuration errors where the inst

Seite 63

QSSC-S4R Technical Product Specification BIOS Initialization 155 16.2.12.2.1.1 Device Location Information The QSSC-S4R system defines memory device

Seite 64

BIOS Initialization QSSC-S4R Technical Product Specification 156CPU4 MEM7_SLOT MEM8_SLOT Table 87. Formats of Memory RAS State SEL Record for Memo

Seite 65 - 7. SAS Riser

QSSC-S4R Technical Product Specification BIOS Initialization 157 Event Data 2 Bits [3:0] Sparing Type When ED2[7:4] = 0000b (Local Sparing Domain)

Seite 66 - 7.2.3 Internal SAS Interface

BIOS Initialization QSSC-S4R Technical Product Specification 158Table 90. Formats of Memory RAS Configuration SEL Record for Memory Sparing Sensor

Seite 67 - 7.2.7 SAS Riser Power

QSSC-S4R Technical Product Specification BIOS Initialization 159 16.2.12.2.2.2 Memory Mismatch and Configuration Errors Table 92. Format of Memory

Seite 68 - 8. Hot Swap Backplane (HSBP)

xviList of Tables Table 1. System Features ...

Seite 69

BIOS Initialization QSSC-S4R Technical Product Specification 16016.2.12.2.2.4 Patrol Scrub Error Records Table 95. Format of Patrol Scrub Error SE

Seite 70

QSSC-S4R Technical Product Specification BIOS Initialization 161 16.2.12.2.3 Memory BIST Error Reporting There are a number of conditions that can

Seite 71 - 8.2 Functional Architecture

BIOS Initialization QSSC-S4R Technical Product Specification 1629. If any DIMM has been marked as disabled for “MemBIST Failure” (does not include

Seite 72 - 8.2.4 SAS Controller

QSSC-S4R Technical Product Specification BIOS Initialization 163 16.2.12.2.6 DIMM Fault Indicator LEDs Intel® Boxboro-EX Chipset server boards that

Seite 73 - 8.2.7.2 SAS Status LEDs

BIOS Initialization QSSC-S4R Technical Product Specification 164The SMI essentially intercepts the MCE, and the BIOS SMI handler reads the Platform

Seite 74 - 2C* Bus IPMB

QSSC-S4R Technical Product Specification BIOS Initialization 165 Intel® MemBIST Uncorrectable Error (if no other good DIMMs are available to continu

Seite 75 - 8.2.12 Programmed Devices

BIOS Initialization QSSC-S4R Technical Product Specification 166

Seite 76 - 9. System Overview

QSSC-S4R Technical Product Specification BIOS Initialization 167 Table 102. Memory ECC Error Handling — Runtime, Non-Redundant Configuration Error

Seite 77

BIOS Initialization QSSC-S4R Technical Product Specification 168Table 103. Memory ECC Error Handling — Runtime, Redundant Configuration Error Scen

Seite 78 - 9.1.1 Fan Subsystem

QSSC-S4R Technical Product Specification BIOS Initialization 169 may vary from boot to boot with varying presence of PCI devices with PCI-PCI bridge

Seite 79 - 9.1.2 Operator Panel

QSSC-S4R Technical Product Specification List of Tables xviiTable 39. Connector Descriptions ...

Seite 80 - 9.3 Power Subsystem

BIOS Initialization QSSC-S4R Technical Product Specification 17016.6.1 Native USB Support During the power-on self test (POST), the BIOS initialize

Seite 81

QSSC-S4R Technical Product Specification BIOS Initialization 171 HW DomainUser Domain OS DomainBeginUser inserts device in the HP-capable PCI Expres

Seite 82

BIOS Initialization QSSC-S4R Technical Product Specification 1725 IOH-2 Gen2 x8 8Gbps PCI Express x8 Slot 5 No 6 IOH-2 Gen2 x8 8Gbps PCI E

Seite 83 - 9.5 Specifications

QSSC-S4R Technical Product Specification BIOS Initialization 173 x Get Fan Configuration: Used to get the SDR records from the BMC. If no profiles

Seite 84 - 9.6 Component Enumeration

BIOS Initialization QSSC-S4R Technical Product Specification 174Byte Name Description3 Record Subtype Value 0Bh Thermal Profile Dat

Seite 85 - 9.6.2 Fans

QSSC-S4R Technical Product Specification BIOS Initialization 175 16.9.1.4 Closed Loop Thermal Throttling (CLTT) QSSC-S4R support Fan Speed Control

Seite 86 - 9.6.5 Memory Riser Boards

BIOS User Interface QSSC-S4R Technical Product Specification 17617. BIOS User Interface 17.1 Splash Logo / Diagnostic Screen The Logo / Diagnostic

Seite 87 - 9.6.8 USB Ports

QSSC-S4R Technical Product Specification BIOS User Interface 177 Table 108. Memory Thermal Throttling OEM SDR bytes 6:N details Functional Area De

Seite 88 - 9.6.9 Power Supply Units

BIOS User Interface QSSC-S4R Technical Product Specification 178+ Change Value The plus key on the keypad is used to change the value of the curre

Seite 89 - 10.1.3 Slide Rails

QSSC-S4R Technical Product Specification BIOS User Interface 179 17.2.3.1 Main Screen The Main screen is the first screen that appears when the BIO

Seite 90 - 10.1.4 Cable Management Arm

xviiiTable 85. Memory RAS Configuration and State SEL Records for Memory Mirroring ... 154Table 86. D

Seite 91 - 10.2.1 Power Supply Modules

BIOS User Interface QSSC-S4R Technical Product Specification 180Setup Item Options Help Text Comments Quiet Boot Enabled Disabled [Enabled] – Di

Seite 92 - 10.2.2 Fan Subsystem

QSSC-S4R Technical Product Specification BIOS User Interface 181 17.2.3.2 Advanced Screen The Advanced screen provides an access point to configure

Seite 93

BIOS User Interface QSSC-S4R Technical Product Specification 18217.2.3.3 Processor Configuration Screen The Processor configuration screen allows

Seite 94 - 10.3 Main Board Subsystem

QSSC-S4R Technical Product Specification BIOS User Interface 183 Table 112. Setup Utility — Processor Configuration Screen Fields Setup Item Opti

Seite 95

BIOS User Interface QSSC-S4R Technical Product Specification 184Setup Item Options (Default in Boldface) Help Text Comments Technology for Direct

Seite 96 - 10.4.1 Hard Drive Carrier

QSSC-S4R Technical Product Specification BIOS User Interface 185 17.2.3.3.1 Memory Configuration Screen The Memory configuration screen allows you

Seite 97 - 10.4.2 Optical Drive

BIOS User Interface QSSC-S4R Technical Product Specification 186Setup Item Options (Default in Boldface) Help Text Comments Speed running at. Me

Seite 98 - 10.4.3 5 ¼” Tape Drive Bay

QSSC-S4R Technical Product Specification BIOS User Interface 187 [Intra-Socket Mirroring] - IMC is mirrored with the other IMC in the same socket.”

Seite 99 - 11. Cables and Connectors

BIOS User Interface QSSC-S4R Technical Product Specification 188Setup Item Options Help Text Comments  Spare Unit: The DDR3 DIMM is functioni

Seite 100

QSSC-S4R Technical Product Specification BIOS User Interface 189 17.2.3.3.5 Serial Port Configuration Screen The Serial Ports Configuration scre

Seite 101 - 11.3.1 Serial Port

QSSC-S4R Technical Product Specification List of Tables xixTable 130. Setup Utility — Hard Disk Order Fields ...

Seite 102 - 11.3.2 Video Ports

BIOS User Interface QSSC-S4R Technical Product Specification 19017.2.3.3.6 USB Configuration Screen The USB Configuration screen allows you to co

Seite 103

QSSC-S4R Technical Product Specification BIOS User Interface 191 devices can be displayed here. USB 2.0 controller Enabled Disabled On-board USB po

Seite 104 - 12. 850W Power Supply

BIOS User Interface QSSC-S4R Technical Product Specification 192Setup Item Options Help Text Comments Warning: If [Disabled] is selected, NIC2 ca

Seite 105 - 12.3 AC Input Requirement

QSSC-S4R Technical Product Specification BIOS User Interface 193 17.2.3.4 Security Screen The Security screen allows you to enable and set the user

Seite 106 - 12.4 DC Output Requirements

BIOS User Interface QSSC-S4R Technical Product Specification 194Setup Item Options Help Text Comments is in the same state as a disabled TPM exc

Seite 107

QSSC-S4R Technical Product Specification BIOS User Interface 195 17.2.3.5 Server Management Screen The Server Management screen allows you to conf

Seite 108 - 12.4.10.3 AC OK

BIOS User Interface QSSC-S4R Technical Product Specification 196Setup Item Options Help Text Comments Detection Disabled play loading of an IPMI

Seite 109 - 13.1 Introduction

QSSC-S4R Technical Product Specification BIOS User Interface 197 To access this screen from the Main screen, select Server Management > System I

Seite 110

BIOS User Interface QSSC-S4R Technical Product Specification 198 Figure 92. Server Management - BMC Configuration Table 125. BMC LAN Configuratio

Seite 111

QSSC-S4R Technical Product Specification BIOS User Interface 199 Setup Item Options Help Text Comments IP source Static Dynamic Select BMC IP s

Seite 112

iiRevision History Date Revision Number Modifications Sept. 14, 2010 1.0 First release Disclaimer Information in this document is provide

Seite 113

xxTable 176. System Status LED Indicator States ...

Seite 114 - 13.2.2 Voltage Regulation

BIOS User Interface QSSC-S4R Technical Product Specification 200 Boot Option #1 <Available Boot devices> Boot Option #2 <Availabl

Seite 115

QSSC-S4R Technical Product Specification BIOS User Interface 201 Disabled based boot options without waiting for user input. USB Boot Priority Enab

Seite 116 - 13.2.10 PMBus Requirements

BIOS User Interface QSSC-S4R Technical Product Specification 20217.2.3.8.1 Add New Boot Option Screen The Add Boot Option screen allows you to add

Seite 117

QSSC-S4R Technical Product Specification BIOS User Interface 203 17.2.3.8.3 Hard Disk Order Screen The Hard Disk Order screen allows you to control

Seite 118

BIOS User Interface QSSC-S4R Technical Product Specification 204Table 131. Setup Utility — CDROM Order Fields Setup Item Options Help Text Comme

Seite 119 - 14.1 Architectural Overview

QSSC-S4R Technical Product Specification BIOS User Interface 205 Table 133. Setup Utility — BEV Device Order Fields Setup Item Options Help Text

Seite 120

BIOS User Interface QSSC-S4R Technical Product Specification 20617.2.3.11 Exit Screen The Exit screen allows you to choose whether to save or disca

Seite 121

QSSC-S4R Technical Product Specification BIOS User Interface 207 17.3 Loading BIOS Defaults Different mechanisms exist for resetting the system con

Seite 122

BIOS Update Support QSSC-S4R Technical Product Specification 20818. BIOS Update Support 18.1 BIOS Update and Recovery One Boot Flash Update refers

Seite 123 - 14.3 Front Panel Control

QSSC-S4R Technical Product Specification Operating System Boot, Sleep, and Wake 209 19. Operating System Boot, Sleep, and Wake 19.1 Boot Device Se

Seite 124

QSSC-S4R Technical Product Specification Introduction 211. Introduction Welcome to the QSSC-S4R Server System Technical Product Specification (TPS)

Seite 125

Operating System Boot, Sleep, and Wake QSSC-S4R Technical Product Specification 21019.1.3 Boot Order Table The BIOS supports the Boot Order Table (

Seite 126 - 15.1 BIOS Architecture

QSSC-S4R Technical Product Specification Operating System Boot, Sleep, and Wake 211 Tables 0 The system Boot Order. 1 Order of devices within fir

Seite 127 - 16. BIOS Initialization

Operating System Boot, Sleep, and Wake QSSC-S4R Technical Product Specification 21219.1.3.3.1 Non-EFI Order Tables A legacy or OEM device order i

Seite 128

QSSC-S4R Technical Product Specification Operating System Boot, Sleep, and Wake 213 19.1.3.3.2 EFI Device Order Table EFI device orders are simi

Seite 129

Operating System Boot, Sleep, and Wake QSSC-S4R Technical Product Specification 21405h Name Varies Null-terminated Unicode string. The string is

Seite 130 - Technology

QSSC-S4R Technical Product Specification Operating System Boot, Sleep, and Wake 215 The BIOS supports ACPI 3.0, 2.0 and 1.0b tables. To prevent con

Seite 131 - Virtualization Technology

Operating System Boot, Sleep, and Wake QSSC-S4R Technical Product Specification 216The wake-up sources are enabled by the ACPI operating systems wi

Seite 132 - 16.1.24 Cbox Error Records

QSSC-S4R Technical Product Specification Operating System Boot, Sleep, and Wake 217 19.2.3.2 WHEA Software Stack The Operating System (OS) kernel

Seite 133 - 16.2 Memory

Operating System Boot, Sleep, and Wake QSSC-S4R Technical Product Specification 218Note: SATA SW RAID and EFI Optimized Boot are mutually exclusiv

Seite 134 - 16.2.2 POST Error Codes

QSSC-S4R Technical Product Specification Operating System Boot, Sleep, and Wake 219 19.4.2 Wake Events / SCI Sources The server board supports the

Seite 135 - 16.2.3.3 ECC Support

Introduction QSSC-S4R Technical Product Specification 22x BMC baseboard management controller Front Control Panel and Operator Panel x System pow

Seite 136 - 16.2.6 Memory Scrub Engine

BIOS Role in Server Management QSSC-S4R Technical Product Specification 22020. BIOS Role in Server Management The BIOS supports many standard-base

Seite 137

QSSC-S4R Technical Product Specification BIOS Role in Server Management 221 x <Esc> followed by a two-second pause must be interpreted as a

Seite 138

BIOS Role in Server Management QSSC-S4R Technical Product Specification 222features and then take control of the system reset or power using the Ch

Seite 139

QSSC-S4R Technical Product Specification BIOS Role in Server Management 223 20.5 System Management BIOS (SMBIOS) The BIOS provides support for the

Seite 140

BIOS Role in Server Management QSSC-S4R Technical Product Specification 224The structure types listed with a table have specific data that is fille

Seite 141

QSSC-S4R Technical Product Specification BIOS Role in Server Management 225 06h Version Byte String Number of the Null-terminated string. This

Seite 142

BIOS Role in Server Management QSSC-S4R Technical Product Specification 226Offset Name Length Value Description0 = Reserved Bits 2:0 0h = Unknown

Seite 143 - 16.2.10.2 Interleaving Mode

QSSC-S4R Technical Product Specification BIOS Role in Server Management 227 Offset Name Length Value Description05h Cache Configuration Byte Varie

Seite 144 - 16.2.10.4 Mirroring Mode

BIOS Role in Server Management QSSC-S4R Technical Product Specification 22804h Count Byte 05 Number of strings. 20.5.2.11 Type 12 Structure — Sy

Seite 145

QSSC-S4R Technical Product Specification BIOS Role in Server Management 229 Offset Name Length Value DescriptionHandle 08h Total Width Word Var

Seite 146 - Copy of Memory Data

QSSC-S4R Technical Product Specification Main Board 232. Main Board 2.1 Introduction The main board provides most of the basic functions for the sys

Seite 147

BIOS Role in Server Management QSSC-S4R Technical Product Specification 23020.5.2.19 Type 38 Structure — IPMI Device Information The SMBIOS Type 3

Seite 148 - 16.2.11 Memory Hot-Plug

QSSC-S4R Technical Product Specification BIOS Role in Server Management 231 20.6 Security 20.6.1 BIOS Setup Password Protection The BIOS uses passw

Seite 149 - 16.2.11.1 Detailed Flow

BIOS Role in Server Management QSSC-S4R Technical Product Specification 232x Measures and stores the boot process in the TPM microcontroller to al

Seite 150

QSSC-S4R Technical Product Specification BIOS Error Handling 233 21. BIOS Error Handling 21.1 Fault Resilient Booting Fault Resilient Booting (FRB

Seite 151

BIOS Error Handling QSSC-S4R Technical Product Specification 234is displayed in the Error Manager if “POST Error Pause” is enabled. In any case, t

Seite 152

QSSC-S4R Technical Product Specification BIOS Error Handling 235 x Errors and warnings detected during POST, and logged as POST errors – these are

Seite 153

BIOS Error Handling QSSC-S4R Technical Product Specification 23621.2.3.1.1 Fatal/Uncorrectable Errors Table 159. Standard AER Fatal Errors Sensor

Seite 154

QSSC-S4R Technical Product Specification BIOS Error Handling 237 Sensor Name Sensor Number SensorType E/RType Sensor-specific Offset ED1 ED2 ED3PC

Seite 155

BIOS Error Handling QSSC-S4R Technical Product Specification 238Sensor Name Sensor Number Sensor Type E/R Type Sensor-specific Offset ED1 ED2 ED3C

Seite 156

QSSC-S4R Technical Product Specification BIOS Error Handling 239 Address Parity errors are errors detected in the memory addressing hardware. Sinc

Seite 157

Main Board QSSC-S4R Technical Product Specification 24x Four independent processor buses x Fully connected sockets (with 4 Intel® QuickPath inter

Seite 158 - Specification

BIOS Error Handling QSSC-S4R Technical Product Specification 240Sensor Name Sensor Number Sensor Type E/R Type Sensor-specific Offset ED1 ED2 ED31

Seite 159

QSSC-S4R Technical Product Specification BIOS Error Handling 241 The BMC logs this event in the SEL, and the system restarts and goes through POST.

Seite 160

BIOS Error Handling QSSC-S4R Technical Product Specification 2420 = ID is IPMB slave address As a result, the generator ID byte will go up in incre

Seite 161

QSSC-S4R Technical Product Specification BIOS Error Handling 243 Progress Code Progress Code Definition0x28 Testing memory PCI Bus 0x50 Enumerat

Seite 162

BIOS Error Handling QSSC-S4R Technical Product Specification 244Progress Code Progress Code Definition0xE0 Started dispatching early initializati

Seite 163

QSSC-S4R Technical Product Specification BIOS Error Handling 245 Note: for 0048 “Password check failed”, the system halts, and then after the next

Seite 164

BIOS Error Handling QSSC-S4R Technical Product Specification 246Error Code Error Message Response 0x84F3 Baseboard Management Controller in Updat

Seite 165

QSSC-S4R Technical Product Specification BIOS Error Handling 247 Table 170. POST Error Beep Codes Beeps Error Message POST Progress Code Descriptio

Seite 166

Baseboard Management Controller (BMC) QSSC-S4R Technical Product Specification 24822. Baseboard Management Controller (BMC) 22.1 Feature Support 2

Seite 167

QSSC-S4R Technical Product Specification Baseboard Management Controller (BMC) 249 x Front panel management: The BMC controls the system status LE

Seite 168 - 16.3.1 Scan Order

QSSC-S4R Technical Product Specification Main Board 252.1.2 Main Board Major Component Placement Figure 2. Main Board Component Locations

Seite 169 - 16.5 Keyboard / Mouse

Baseboard Management Controller (BMC) QSSC-S4R Technical Product Specification 250x 250 MHz 32-bit ARM9 Processor x Memory Management Unit (MMU)

Seite 170 - 16.8 PCI Express Hot Plug

QSSC-S4R Technical Product Specification BMC Functional Specifications 251 23. BMC Functional Specifications 23.1 Power System The BMC is in-line

Seite 171 - ACPI-assisted Hot-plug

BMC Functional Specifications QSSC-S4R Technical Product Specification 252must also coincide with the assertion of the “CPU Power Failure Status” b

Seite 172 - 16.9.1.2 Fan Profile Option

QSSC-S4R Technical Product Specification BMC Functional Specifications 253 23.1.5.1 Power Button Signal The POWER_BUTTON signal is filtered through

Seite 173

BMC Functional Specifications QSSC-S4R Technical Product Specification 254x The watchdog timer is stopped. x The power, reset, front panel NMI, a

Seite 174

QSSC-S4R Technical Product Specification BMC Functional Specifications 255 BMC reset IPMI command No Yes 23.3.3 Front Panel System Reset The rese

Seite 175 - C reads this using PECI)

BMC Functional Specifications QSSC-S4R Technical Product Specification 256After the BIOS has identified and saved the BSP information, it sets the

Seite 176 - 17. BIOS User Interface

QSSC-S4R Technical Product Specification Processor Presence and Population Check 257 24. Processor Presence and Population Check 24.1.1 BSP Identi

Seite 177 - 17.2.2.2 Keyboard Commands

Processor Presence and Population Check QSSC-S4R Technical Product Specification 258When AC power is first applied to the system, the status LED wi

Seite 178 - 17.2.2.3 Menu Selection Bar

QSSC-S4R Technical Product Specification Processor Presence and Population Check 259 24.2.3 Chassis ID LED The chassis ID LED provides a visual ind

Seite 179 - 17.2.3.1 Main Screen

Main Board QSSC-S4R Technical Product Specification 26Table 2. Mainboard components Item Component Type # Description A CPU/socket 1 – 4

Seite 180

Processor Presence and Population Check QSSC-S4R Technical Product Specification 26024.2.5 Secure Mode and Front Panel Lock-out Operation The front

Seite 181 - 17.2.3.2 Advanced Screen

QSSC-S4R Technical Product Specification Processor Presence and Population Check 261 24.5 BMC Internal Timestamp Clock The BMC maintains a four-byt

Seite 182

Processor Presence and Population Check QSSC-S4R Technical Product Specification 262regardless of the system power state The BMC allocates 65,519 b

Seite 183

QSSC-S4R Technical Product Specification Processor Presence and Population Check 263 06 1 A0h Memory Riser Board E RW 256 07 1 A2h Memory Rise

Seite 184

Processor Presence and Population Check QSSC-S4R Technical Product Specification 264Table 178. NMI Signal Generation and Event Logging Causal Event

Seite 185

QSSC-S4R Technical Product Specification Processor Presence and Population Check 265 Table 179. Processor Sensors Sensor Name Per Per-Proc Socket

Seite 186

Processor Presence and Population Check QSSC-S4R Technical Product Specification 266Upon BMC initialization, the processor presence offset is initi

Seite 187

QSSC-S4R Technical Product Specification Processor Presence and Population Check 267 The BMC provides 10-bit A/Ds for voltage monitoring. The BMC F

Seite 188

Processor Presence and Population Check QSSC-S4R Technical Product Specification 268the fan speed sensors and clears fan failure conditions. If the

Seite 189

QSSC-S4R Technical Product Specification Processor Presence and Population Check 269 Such oscillation can be prevented by specifying positive or ne

Seite 190

QSSC-S4R Technical Product Specification Main Board 27H External USB Rear: 2x4-pin double stacked USB2.0 connector I IO Riser Slot Designated

Seite 191

Processor Presence and Population Check QSSC-S4R Technical Product Specification 270the table lookup is saved for reference. When the final domain

Seite 192

QSSC-S4R Technical Product Specification Processor Presence and Population Check 271 24.13.4.3 Sensor Failure Each Tcontrol SDR sub-record has a fa

Seite 193 - 17.2.3.4 Security Screen

Processor Presence and Population Check QSSC-S4R Technical Product Specification 27224.13.5.2 ASHRAE Compliance System requirements for ASHRAE comp

Seite 194

QSSC-S4R Technical Product Specification Processor Presence and Population Check 273 In order for the BMC to handle these values in its fan speed c

Seite 195

Processor Presence and Population Check QSSC-S4R Technical Product Specification 274AND x Processor VR current trip point (default setting: 90% of

Seite 196

QSSC-S4R Technical Product Specification Processor Presence and Population Check 275 x During runtime, if BIOS needs to return bus ownership to th

Seite 197

Processor Presence and Population Check QSSC-S4R Technical Product Specification 276 Figure 109. BMC/BIOS interactions for Memory Hot-Plug/On-line/

Seite 198

QSSC-S4R Technical Product Specification Processor Presence and Population Check 277 3. Exit firmware transfer mode (BMC reset) will cause LED to s

Seite 199 - 17.2.3.8 Boot Options Screen

Processor Presence and Population Check QSSC-S4R Technical Product Specification 278Power Supply 2 B2h Power Supply 3 B4h Power Supply 4 B6h 24.

Seite 200

QSSC-S4R Technical Product Specification Processor Presence and Population Check 279 power is applied to the system and the previous system power s

Seite 201

Main Board QSSC-S4R Technical Product Specification 28800/1067 memory technologies. It uses a power-through-the-pins power delivery system and LS s

Seite 202

Processor Presence and Population Check QSSC-S4R Technical Product Specification 280Power supply fan sensors are implemented as manual re-arm senso

Seite 203

QSSC-S4R Technical Product Specification Processor Presence and Population Check 281 70 80 90 100% 80% 80% 100 100% 80% 80% 4. HSC Temp: Apart fro

Seite 204

Processor Presence and Population Check QSSC-S4R Technical Product Specification 28224.25.6 Power Unit Redundancy The BMC supports redundant power

Seite 205

QSSC-S4R Technical Product Specification Processor Presence and Population Check 283 Table 188 shows outputs that can be tested via the Set SM Sign

Seite 206 - 17.2.3.11 Exit Screen

Processor Presence and Population Check QSSC-S4R Technical Product Specification 284DIMM DIMM Map for CPU Group 0, Riser 1 CPU Group 1, Riser 3 C

Seite 207 - 17.3 Loading BIOS Defaults

QSSC-S4R Technical Product Specification Processor Presence and Population Check 285 All processors in a system have their CATERR pins tied togethe

Seite 208 - 18. BIOS Update Support

BMC Messaging Interfaces QSSC-S4R Technical Product Specification 28625. BMC Messaging Interfaces This chapter describes the supported BMC communi

Seite 209 - 19.1 Boot Device Selection

QSSC-S4R Technical Product Specification BMC Messaging Interfaces 287 1. User names for User IDs 1 and 2 cannot be changed. These will always be ““

Seite 210 - 19.1.3 Boot Order Table

BMC Messaging Interfaces QSSC-S4R Technical Product Specification 288But,  (per channel session limit) (bullet 4) > (total session slots) (bull

Seite 211

QSSC-S4R Technical Product Specification BMC Messaging Interfaces 289 25.6.2 Receive Message Queue The receive message queue is only accessible via

Seite 212 - Name Length Description

QSSC-S4R Technical Product Specification Main Board 292.2.1.4 Rbox: Intel® QuickPath Interconnect Router The Intel® Xeon® Rbox is an eight-port rou

Seite 213 - 19.1.3.4 BOT Device Name(s)

BMC Messaging Interfaces QSSC-S4R Technical Product Specification 290x An event is in the event message buffer x Watchdog pre-timeout interrupt fla

Seite 214

QSSC-S4R Technical Product Specification BMC Messaging Interfaces 291 25.7.2 IPMB LUN Routing The BMC can receive either request or response IPMB me

Seite 215 - Power Interface Specification

BMC Messaging Interfaces QSSC-S4R Technical Product Specification 292Figure 110. BMC IPMB Message Reception 25.8 IPMI Serial Feature The IPMI 2.0 I

Seite 216 - 19.2.3.1 WHEA Overview

QSSC-S4R Technical Product Specification BMC Messaging Interfaces 293 25.8.2.2.2 Hex-ASCII Commands The BMC supports the IPMI binary commands speci

Seite 217 - 19.2.4 EFI Optimized Boot

BMC Messaging Interfaces QSSC-S4R Technical Product Specification 294IPMI 2.0 messaging introduces payload types and payload IDs to allow data type

Seite 218 - 19.4 Sleep and Wake Support

QSSC-S4R Technical Product Specification BMC Messaging Interfaces 295 25.9.5.1.1 Static LAN Configuration Parameters When the IP Address Configur

Seite 219

BMC Messaging Interfaces QSSC-S4R Technical Product Specification 296x When Block Size < 16, it must be the last Block request in this series.

Seite 220 - 20.2 Console Redirection

QSSC-S4R Technical Product Specification BMC Messaging Interfaces 297 25.9.12 Platform Event Filter (PEF) The BMC includes the ability to generate a

Seite 221 - 20.3 IPMI Serial Interface

BMC Messaging Interfaces QSSC-S4R Technical Product Specification 298provides a text string that describes a simple description of the event. SMTP

Seite 222 - Use Case Model

QSSC-S4R Technical Product Specification BMC Flash Update 299 26. BMC Flash Update 26.1 Logical Firmware Image Blocks The BMC firmware is divided

Seite 223 - 20.5.1 Access Methods

QSSC-S4R Technical Product Specification Contents iii Contents 1. Introduction ...

Seite 224 - Length Value Description

Main Board QSSC-S4R Technical Product Specification 302.2.2 Intel® 7500 Chipset The Intel® 7500 Chipset (Boxboro I/O Hub) component provides a conn

Seite 225 - Definition

BMC Flash Update QSSC-S4R Technical Product Specification 300Firmware Transfer commands allow any area of the BMC flash to be updated. These functi

Seite 226 - Length Value Description

QSSC-S4R Technical Product Specification BMC Flash Update 301 The jumper is normally in the de-asserted position. The system must be completely pow

Seite 227

BIOS-BMC Interactions QSSC-S4R Technical Product Specification 30227. BIOS-BMC Interactions BIOS-BMC interactions include the following: x FRB2 Ope

Seite 228

QSSC-S4R Technical Product Specification BMC-HSC Interactions 303 28. BMC-HSC Interactions 28.1 HSC Availability QSSC-S4R supports Hot-Swap Controll

Seite 229

Sensors QSSC-S4R Technical Product Specification 30429. Sensors Specific server boards may only implement a sub-set of sensors and / or may include

Seite 230

QSSC-S4R Technical Product Specification Sensors 305 Default Hysteresis x The hysteresis setting applies to all thresholds of the sensor. This colu

Seite 231 - 20.6 Security

Sensors QSSC-S4R Technical Product Specification 306Table 202. IBMC Core Sensors Full Sensor Name (Sensor name in SDR) Sensor # Sensor Type Even

Seite 232 - 20.6.3.2 Physical Presence

QSSC-S4R Technical Product Specification Sensors 307 Full Sensor Name (Sensor name in SDR) Sensor # Sensor Type Event / Reading Type Event Offset

Seite 233 - 21. BIOS Error Handling

Sensors QSSC-S4R Technical Product Specification 308Full Sensor Name (Sensor name in SDR) Sensor # Sensor Type Event / Reading Type Event Offset

Seite 234 - 21.1.4 Boot Event

QSSC-S4R Technical Product Specification Sensors 309 Full Sensor Name (Sensor name in SDR) Sensor # Sensor Type Event / Reading Type Event Offset

Seite 235 - 21.2.2 NMI on Fatal Errors

QSSC-S4R Technical Product Specification Main Board 31 Figure 3 Intel® 7500 Chipset High-Level Block Diagram 2.2.2.2 Intel® QPI Features Two full-wi

Seite 236 - ED1 ED2 ED3

Sensors QSSC-S4R Technical Product Specification 310Full Sensor Name (Sensor name in SDR) Sensor # Sensor Type Event / Reading Type Event Offset

Seite 237

QSSC-S4R Technical Product Specification Sensors 311 Full Sensor Name (Sensor name in SDR) Sensor # Sensor Type Event / Reading Type Event Offset

Seite 238 - 21.2.3.3 Memory Sensors

Sensors QSSC-S4R Technical Product Specification 312Full Sensor Name (Sensor name in SDR) Sensor # Sensor Type Event / Reading Type Event Offset

Seite 239

QSSC-S4R Technical Product Specification Hot-Swap Controller (HSC) Architecture 313 30. Hot-Swap Controller (HSC) Architecture The HSC uses a VSC4

Seite 240 - 21.2.3.6.2 OS Boot timeout

HSC Functional Specifications QSSC-S4R Technical Product Specification 31431. HSC Functional Specifications 31.1 Platform Determination The HSC pr

Seite 241 - 21.2.3.7 Boot Event

QSSC-S4R Technical Product Specification HSC Functional Specifications 315 Table 206. Cable Detect Configuration Cable A Detected Cable B Detected

Seite 242 - 21.3.2 POST Code Checkpoints

HSC Functional Specifications QSSC-S4R Technical Product Specification 31631.7 Disk Management 31.7.1 Drive Fault Light Control The HSC activates a

Seite 243

QSSC-S4R Technical Product Specification HSC IPMB Application and Sensors 317 32. HSC IPMB Application and Sensors This section presents the addit

Seite 244

HSC IPMB Application and Sensors QSSC-S4R Technical Product Specification 318Drive Slot 5 Presence 0Fh Drive Slot (0Dh) 08h Presence auto dev. r

Seite 245

QSSC-S4R Technical Product Specification HSC Firmware Update 319 33. HSC Firmware Update The HSC firmware is stored in a separate SPI-compatible EE

Seite 246 - 21.3.4 POST Error Beep Codes

Main Board QSSC-S4R Technical Product Specification 32x8. If that attempt fails, an attempt is made at x4, then at x2 and finally at x1. Note that

Seite 247

HSC Firmware Update QSSC-S4R Technical Product Specification 320Glossary This appendix contains important terms used in the preceding chapters. For

Seite 248 - 22.1 Feature Support

QSSC-S4R Technical Product Specification HSC Firmware Update 321 LAN Local Area Network LED Light Emitting Diode LPC Low Pin Count LVDS Low Volta

Seite 249

HSC Firmware Update QSSC-S4R Technical Product Specification 322Reference Documents

Seite 250 - C interfaces

QSSC-S4R Technical Product Specification Main Board 33 Figure 14. QSSC-S4R Memory Riser Functional Block Diagram and DIMM Population Rules Intel® 7

Seite 251 - 23.1 Power System

Main Board QSSC-S4R Technical Product Specification 342.3.1.1 Enterprise South Bridge Interface (ESI) Enterprise South Bridge Interface (ESI) is t

Seite 252 - 23.1.5 Power Control Sources

QSSC-S4R Technical Product Specification Main Board 35The timer/counter block contains three counters that are equivalent in function to those found

Seite 253 - 23.1.8 Wake-On-LAN (WOL)

Main Board QSSC-S4R Technical Product Specification 36applications to run in independent partitions. A partition behaves like a virtual machine (VM

Seite 254 - 23.3 System Reset Control

QSSC-S4R Technical Product Specification Main Board 37The main board includes a 300 pin PCI Express super-slot custom connector to interface with th

Seite 255 - 23.5 System Initialization

Main Board QSSC-S4R Technical Product Specification 38generates 100MHz SRC clocks including an input to a DB1200 buffer to I/O subsystems. Figure

Seite 256

QSSC-S4R Technical Product Specification Main Board 39 Figure 4. Main Board Clock Block Diagram CK410B supports SSC (Spread Spectrum Clocking) and S

Seite 257 - 24.1.1 BSP Identification

iv3.3.5 Chassis Intrusion ...

Seite 258

Main Board QSSC-S4R Technical Product Specification 402.3.6.1.2 DB1200 PCI Express Clock Buffer DB1200 Version 2.0 device with PCI Express Gen2 su

Seite 259 - 24.2.3 Chassis ID LED

QSSC-S4R Technical Product Specification Main Board 412.3.10 Post Code LEDs Eight light emitting diodes are used to indicate the raw binary output o

Seite 260 - 24.4 Watchdog Timer

Main Board QSSC-S4R Technical Product Specification 42x After CPU and VTT VRs are enabled, as well as any memory riser presence signal asserted, a

Seite 261 - 24.6 System Event Log (SEL)

QSSC-S4R Technical Product Specification Main Board 43 Figure 7. Mainboard Power Block Diagram

Seite 262 - 24.8.2 BMC FRU ID Mapping

Main Board QSSC-S4R Technical Product Specification 442.3.14 Reset and Powergood Diagram Figure 8. Main Board Reset and Powergood Block Diagram

Seite 263 - 24.9.1 Signal Generation

QSSC-S4R Technical Product Specification Main Board 452.3.15 Power Sequencing/Timing Diagrams Figure 9. Main Board Power Sequencing Diagram 2.3.1

Seite 264 - 24.11 Processor Sensors

Main Board QSSC-S4R Technical Product Specification 46Table 7. QSSC-S4R Thermal Specification Component Target Velocity Target Ambient Temp Spec

Seite 265 - 24.11.1.1 Processor Presence

QSSC-S4R Technical Product Specification Main Board Server Management 473. Main Board Server Management 3.1 Introduction The QSSC-S4R Server Manage

Seite 266 - 24.12 Voltage Monitoring

Main Board Server Management QSSC-S4R Technical Product Specification 48x System event log (SEL) device functionality: The BMC supports and provid

Seite 267 - 24.13.1 Hot Swap Fans

QSSC-S4R Technical Product Specification Main Board Server Management 493.2 Functional Architecture 3.2.1 Server Management Block Diagram Figure 1

Seite 268 - 24.13.4 Nominal Fan Speed

QSSC-S4R Technical Product Specification Contents v 9.1 External Chassis Features – Front ...

Seite 269 - 24.13.4.1.2 Domain Maximum

Main Board Server Management QSSC-S4R Technical Product Specification 503.2.2 SMBus Block Diagram Figure 11. SMBus Block Diagram

Seite 270 - 24.13.4.2 Clamp

QSSC-S4R Technical Product Specification Main Board Server Management 513.2.3 Hardware Monitoring Block Diagram Figure 12. Hardware Monitoring Blo

Seite 271 - 24.13.5.1 Fan Profiles

Main Board Server Management QSSC-S4R Technical Product Specification 520E 4 A6h Power Supply 4 RO 256 0F 5 AEh Front Panel Fan Board RW 25

Seite 272 - 24.13.5.2 ASHRAE Compliance

QSSC-S4R Technical Product Specification Main Board Server Management 53x All 4x power supplies are not installed in the system OR multiple power

Seite 273 - 24.18 Power Throttle Sensor

Memory Riser QSSC-S4R Technical Product Specification 544. Memory Riser The QSSC-S4R Server System supports up to eight memory riser modules that p

Seite 274 - 24.20.1 Semaphore Operation

QSSC-S4R Technical Product Specification Memory Riser 55Figure 14. QSSC-S4R Memory Riser Functional Block Diagram and DIMM Population Rules 4.2 Int

Seite 275

Memory Riser QSSC-S4R Technical Product Specification 564.2.2 DDR3 Functionality Figure 15. DDR3 Interlace Block Diagram DDR3 protocol and signali

Seite 276 - 24.21 HeartBeat LED

QSSC-S4R Technical Product Specification Memory Riser 574.3 Functional Architecture Figure 16 Memory Riser Block Diagram 4.3.1 Supported Memory Co

Seite 277 - 24.23 Global Fan Fault LED

Memory Riser QSSC-S4R Technical Product Specification 58x Sx - Indicates that the CPU socket is populated. S0 is CPU socket 1, S1 is CPU socket 2,

Seite 278 - 24.25 Power Unit Management

QSSC-S4R Technical Product Specification I/O Riser 595. I/O Riser 5.1 I/O Riser Features The I/O riser board provides most of the systems rear I/O i

Seite 279 - 24.25.1.4 Power Unit Failure

vi12.4.2 Output Current Rating ...

Seite 280 - IPMI Sensor Characteristics

I/O Riser QSSC-S4R Technical Product Specification 605.2 Functional Architecture Figure 17. I/O Riser Block Diagram 5.3 Video Subsystem 5.3.1 Fea

Seite 281 - Event Logging

QSSC-S4R Technical Product Specification I/O Riser 615.3.2 ServerEngines Pilot II IBMC Block Diagram Figure 18. ServerEngines* Pilot II IBMC Block

Seite 282 - 24.30 BMC Test Commands

I/O Riser QSSC-S4R Technical Product Specification 62Pilot includes two USB interfaces. The USB0 is a dedicated USB2.0 interface and the USB1 is th

Seite 283

QSSC-S4R Technical Product Specification Intel® Remote Management Module 3 (RMM3) 636. Intel® Remote Management Module 3 (RMM3) This 1.23” x 2.30”

Seite 284 - 24.34 CATERR Reporting

Intel® Remote Management Module 3 (RMM3) QSSC-S4R Technical Product Specification 64y Mouse tracking and synchronization. It allows remote viewing

Seite 285

QSSC-S4R Technical Product Specification SAS Riser 657. SAS Riser 7.1 Introduction The SAS riser works in conjunction with the Hot-swap Backplane (

Seite 286

SAS Riser QSSC-S4R Technical Product Specification 66 Figure 20. SAS Riser Board System Block Diagram 7.2.1 I²C Interface The SAS Riser board cont

Seite 287 - 25.3 Sessions

QSSC-S4R Technical Product Specification SAS Riser 67 Figure 21. SAS Riser Board Placement View The sideband signals are configured to adhere to the

Seite 288 - 25.4 Media Bridging

Hot Swap Backplane (HSBP) QSSC-S4R Technical Product Specification 688. Hot Swap Backplane (HSBP) 8.1 Introduction The Hot Swap Backplane (HSBP) pr

Seite 289 - 25.6.2 Receive Message Queue

QSSC-S4R Technical Product Specification Hot Swap Backplane (HSBP) 698.1.2 Placement View and LED Definition The following section describes major

Seite 290 - C Master Controller on IPMB

QSSC-S4R Technical Product Specification Contents vii16.1.12 Enhanced Intel SpeedStep® Technology ...

Seite 291 - 25.7.2 IPMB LUN Routing

Hot Swap Backplane (HSBP) QSSC-S4R Technical Product Specification 70 Table 14. 8X HDD Activity LED Functionality on the HSBP Condition Drive Type

Seite 292 - 25.8.2 Terminal Mode

QSSC-S4R Technical Product Specification Hot Swap Backplane (HSBP) 718.1.3.5 HSBP SGPIO Connectors Table 19. 1x6-pin HSBP SATA SGPIO A – Signal Des

Seite 293 - 25.9 LAN Interface

Hot Swap Backplane (HSBP) QSSC-S4R Technical Product Specification 72 Figure 24. HSBP System Block Diagram 8.2.1 SAS Buses The SAS buses are direct

Seite 294 - 25.9.3 RMCP / ASF Messaging

QSSC-S4R Technical Product Specification Hot Swap Backplane (HSBP) 738.2.5 Vitesse* VSC410 Controller Functionality The Vitesse* VSC410 is a storag

Seite 295 - 25.9.6 DHCP BMC Hostname

Hot Swap Backplane (HSBP) QSSC-S4R Technical Product Specification 748.2.8 SAS Enclosure Management SAS enclosure management allows the Hot-swap Ba

Seite 296

QSSC-S4R Technical Product Specification Hot Swap Backplane (HSBP) 75AT24C64* 0xA0 VSC local bus Private SAS backplane FRU EEPROM TPM75 0x90 V

Seite 297

System Overview QSSC-S4R Technical Product Specification 769. System Overview QSSC-S4R is a 4U rack mount server that supports four CPU sockets (In

Seite 298

QSSC-S4R Technical Product Specification System Overview 77Item Description A Optical Drive B Rear LAN LEDs (from I/O Riser) C Operator Panel D Vid

Seite 299 - 26. BMC Flash Update

System Overview QSSC-S4R Technical Product Specification 78x Control the front panel I/O providing the end user access to the system video, USB in

Seite 300 - 26.3 Boot Recovery Mode

QSSC-S4R Technical Product Specification System Overview 79The fans are docked on the front panel fan board (FPFB). Each fan module has an amber LED

Seite 301

viii18. BIOS Update Support ... 20818.1 BIOS

Seite 302 - 27. BIOS-BMC Interactions

System Overview QSSC-S4R Technical Product Specification 80Figure 32. System Rear (Enterprise SKU shown) Table 25. System rear items and descriptio

Seite 303 - 28. BMC-HSC Interactions

QSSC-S4R Technical Product Specification System Overview 81NOTE: Refer to Tables below for maximum DC loading for both AC redundant and AC non redun

Seite 304 - 29. Sensors

System Overview QSSC-S4R Technical Product Specification 82Optical Device Yes Yes No 5.25” Tape Device Yes Yes No Power Supply 2+2 3+1 2+0 12V Avai

Seite 305

QSSC-S4R Technical Product Specification System Overview 83protection circuitry for one of the outputs and a FRU EEPROM. It also routes PMBus I2C si

Seite 306 - Table 202. IBMC Core Sensors

System Overview QSSC-S4R Technical Product Specification 84Immunity Verified to comply with EN55024, CISPR 24, GOST-R Electrostatic discharge Tes

Seite 307 - Contrib. To

QSSC-S4R Technical Product Specification System Overview 85 9.6.2 Fans Eight fans are located at the upper front of the system for general cooling

Seite 308

System Overview QSSC-S4R Technical Product Specification 869.6.3 Hard Drive Slots The hard drive slots are numbered zero through seven starting fro

Seite 309

QSSC-S4R Technical Product Specification System Overview 87 9.6.7 NIC Ports The Quad-Gigabit Ethernet ports on the I/O riser board are numbered from

Seite 310

System Overview QSSC-S4R Technical Product Specification 88 9.6.9 Power Supply Units The power bay provides space for four power supply modules and

Seite 311

QSSC-S4R Technical Product Specification System Chassis and Sub-Assemblies 8910. System Chassis and Sub-Assemblies 10.1 Base Chassis and Top Cover

Seite 312

QSSC-S4R Technical Product Specification Contents ix 21.2.4 Logging Format Conventions ...

Seite 313 - 30.1.3 GPIO Pins

System Chassis and Sub-Assemblies QSSC-S4R Technical Product Specification 90Figure 33. Slide Rail Mounting Features Figure 34. Slide Rail mounted

Seite 314 - 31.2 System Initialization

QSSC-S4R Technical Product Specification System Chassis and Sub-Assemblies 91 Figure 36. Power Supply Unit (PSU) 10.2.1 Power Supply Modules The ou

Seite 315 - 31.6 Temperature Monitoring

System Chassis and Sub-Assemblies QSSC-S4R Technical Product Specification 92 Figure 37. Power Supply Indicators Note: The cooling system is non-re

Seite 316 - 31.7 Disk Management

QSSC-S4R Technical Product Specification System Chassis and Sub-Assemblies 93 Figure 38. Fan Location Figure 39. S4R Fan Module In addition, there

Seite 317 - 32.2 Sensors

System Chassis and Sub-Assemblies QSSC-S4R Technical Product Specification 9410.2.2.2 Fan Module Functional Block Diagram Figure 40. Fan Module F

Seite 318

QSSC-S4R Technical Product Specification System Chassis and Sub-Assemblies 95 Figure 41. Main Board Mount Structure & Strengthened CPU Heat-sin

Seite 319 - 33. HSC Firmware Update

System Chassis and Sub-Assemblies QSSC-S4R Technical Product Specification 96x CPU heat-sink dividers isolate the flow channels through each CPU a

Seite 320 - Glossary

QSSC-S4R Technical Product Specification System Chassis and Sub-Assemblies 97Caution To ensure proper airflow and server cooling, all drive bays m

Seite 321

System Chassis and Sub-Assemblies QSSC-S4R Technical Product Specification 9810.4.3 5 ¼” Tape Drive Bay The system includes a bay that can support

Seite 322 - Reference Documents

QSSC-S4R Technical Product Specification Cables and Connectors 9911. Cables and Connectors This section describes interconnections between the vari

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