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QSSC-S4R Technical Product Specification BIOS Initialization
175
16.9.1.4 Closed Loop Thermal Throttling (CLTT)
QSSC-S4R support Fan Speed Control (FSC) in Closed Loop Thermal Throttling (CLTT) fashion. OLTT is NOT
supported. CLTT is enabled by default by BIOS. Also in QSSC-S4R only RDIMM are supported. If RDIMM with a failed
Thermal Sensor is detected CLTT will not be enabled and BIOS error manager will show that error.
For a very detailed description on the thermal sensors, thermal zones, zone aggregation and fan domains please refer
to the QSSC-S4R Fan Speed Control and Thermal Management Platform Architecture Specification, rev 1.0.
16.9.2 Processor Thermal Management
The processors implement a methodology for managing processor temperatures through processor throttling. The
temperature used to regulate the processors is calculated using the following two components:
x Tcontrol offset (BMC reads this using PECI).
x Tcontrol base (BMC retrieves this value from SDR).
The BMC uses these two Tcontrol values to regulate processor thermal characteristics according to the user-selected
fan profile.
See the
Nehalem Processor Family BIOS Writer’s Guide for more information.
16.9.3 Node Power Thermal Management (NPTM) or Node Manager (NM)
The QSSC-S4R BIOS has set up Intel
®
Intelligent Power Node Manager 1.5 compatible interfaces to allow greater
processor thermal and power control.
- Contents 3
- List of Figures 13
- List of Tables 16
- 1. Introduction 21
- 2. Main Board 23
- 2.2 Functional Architecture 27
- 2.2.2 Intel® 7500 Chipset 30
- 2.2.2.2 Intel® QPI Features 31
- 2.2.2.5 Controller Link (CL) 32
- 2.3.1 ICH10R Southbridge 33
- 2.3.2 PCI-Express Subsystem 36
- 2.3.6 Clock Subsystem 37
- 2.3.6.1.1 CK MNG 39
- 2.3.8 BIOS Flash Devices 40
- 2.3.9 USB 2.0 Subsystem 40
- 2.3.10 Post Code LEDs 41
- 3.1 Introduction 47
- 3.1.2 Non IPMI Features 48
- 3.2 Functional Architecture 49
- 3.2.2 SMBus Block Diagram 50
- 3.3 Supported Features 52
- 3.3.4 Memory Throttling 53
- 3.3.5 Chassis Intrusion 53
- 4. Memory Riser 54
- ® SMI Status Frame 55
- 4.2.2 DDR3 Functionality 56
- 4.3 Functional Architecture 57
- 4.3.3 Memory Riser LEDs 58
- 4.3.4 Power Rails 58
- 5. I/O Riser 59
- 5.2 Functional Architecture 60
- 5.3 Video Subsystem 60
- 5.4 USB Subsystem 61
- 7. SAS Riser 65
- 7.2.1 I²C Interface 66
- 7.2.2 Host Interface 66
- 7.2.3 Internal SAS Interface 66
- 7.2.4 Memory Interface 67
- 7.2.5 Debug Jumpers 67
- 7.2.7 SAS Riser Power 67
- 8. Hot Swap Backplane (HSBP) 68
- 8.2 Functional Architecture 71
- 8.2.1 SAS Buses 72
- 8.2.2 Hot-swap Backplane 72
- 8.2.4 SAS Controller 72
- 8.2.5.1 SPI Flash 73
- 8.2.7.2 SAS Status LEDs 73
- 2C* Interface 74
- 2C* Bus 74
- 2C* Bus IPMB 74
- 8.2.10 Resets 75
- 8.2.11 Clock Generation 75
- 8.2.12 Programmed Devices 75
- 9. System Overview 76
- 9.1.1 Fan Subsystem 78
- 9.1.2 Operator Panel 79
- 9.3 Power Subsystem 80
- 9.4 Cooling Subsystem 83
- 9.5 Specifications 83
- 9.6 Component Enumeration 84
- 9.6.2 Fans 85
- 9.6.3 Hard Drive Slots 86
- 9.6.4 PCIe Slots 86
- 9.6.5 Memory Riser Boards 86
- 9.6.7 NIC Ports 87
- 9.6.8 USB Ports 87
- 9.6.9 Power Supply Units 88
- 10.1.1 Base Chassis 89
- 10.1.2 Top Cover 89
- 10.1.3 Slide Rails 89
- 10.1.4 Cable Management Arm 90
- 10.2.1 Power Supply Modules 91
- 10.2.2 Fan Subsystem 92
- 10.3 Main Board Subsystem 94
- 10.4.1 Hard Drive Carrier 96
- 10.4.2 Optical Drive 97
- 10.4.3 5 ¼” Tape Drive Bay 98
- 11. Cables and Connectors 99
- 11.3.1 Serial Port 101
- 11.3.2 Video Ports 102
- 12. 850W Power Supply 104
- 12.3 AC Input Requirement 105
- 12.4 DC Output Requirements 106
- 12.4.10.1 Power Supply Fail 108
- 12.4.10.2 Power Good 108
- 12.4.10.3 AC OK 108
- 13.1 Introduction 109
- 13.2.2 Voltage Regulation 114
- 13.2.10 PMBus Requirements 116
- 14.1 Architectural Overview 119
- 14.3 Front Panel Control 123
- 15.1 BIOS Architecture 126
- 16. BIOS Initialization 127
- Technology 130
- Virtualization Technology 131
- 16.1.24 Cbox Error Records 132
- 16.2 Memory 133
- 16.2.2 POST Error Codes 134
- 16.2.3.2 High-Memory Reclaim 135
- 16.2.3.3 ECC Support 135
- 16.2.5 Memory Test 136
- 16.2.6 Memory Scrub Engine 136
- 16.2.10.1 Lock Step Mode 143
- 16.2.10.2 Interleaving Mode 143
- 16.2.10.3 Sparing Mode 144
- 16.2.10.4 Mirroring Mode 144
- Copy of Memory Data 146
- 16.2.11 Memory Hot-Plug 148
- 16.2.11.1 Detailed Flow 149
- Specification 158
- 16.3.1 Scan Order 168
- 16.4 PnP ISA 169
- 16.5 Keyboard / Mouse 169
- 16.7 Removable Media Drives 170
- 16.8 PCI Express Hot Plug 170
- HW Domain 171
- User Domain OS Domain 171
- Native Hot-plug 171
- OS Domain 171
- ACPI-assisted Hot-plug 171
- 16.9.1.2 Fan Profile Option 172
- C reads this using PECI) 175
- 17. BIOS User Interface 176
- 17.2.2.2 Keyboard Commands 177
- 17.2.2.3 Menu Selection Bar 178
- 17.2.3.1 Main Screen 179
- 17.2.3.2 Advanced Screen 181
- 17.2.3.4 Security Screen 193
- 17.2.3.8 Boot Options Screen 199
- 17.2.3.11 Exit Screen 206
- 17.3 Loading BIOS Defaults 207
- 18. BIOS Update Support 208
- 19.1 Boot Device Selection 209
- 19.1.3 Boot Order Table 210
- Name Length Description 212
- 19.1.3.4 BOT Device Name(s) 213
- Power Interface Specification 215
- 19.2.3.1 WHEA Overview 216
- 19.2.4 EFI Optimized Boot 217
- 19.4 Sleep and Wake Support 218
- 20.1 IPMI 220
- 20.2 Console Redirection 220
- 20.3 IPMI Serial Interface 221
- Use Case Model 222
- 20.5.1 Access Methods 223
- Length Value Description 224
- Definition 225
- Length Value Description 226
- 20.6 Security 231
- 20.6.3.2 Physical Presence 232
- 21. BIOS Error Handling 233
- 21.1.4 Boot Event 234
- 21.2.2 NMI on Fatal Errors 235
- ED1 ED2 ED3 236
- 21.2.3.2 Legacy PCI Sensors 238
- 21.2.3.3 Memory Sensors 238
- 21.2.3.6.2 OS Boot timeout 240
- 21.2.3.7 Boot Event 241
- 21.3.1 Diagnostic LEDs 242
- 21.3.2 POST Code Checkpoints 242
- 21.3.4 POST Error Beep Codes 246
- 22.1 Feature Support 248
- C interfaces 250
- 23.1 Power System 251
- 23.1.3 Power up Sequence 252
- 23.1.4 Power Down Sequence 252
- 23.1.5 Power Control Sources 252
- 23.1.6 Power State Retention 253
- 23.1.8 Wake-On-LAN (WOL) 253
- 23.3 System Reset Control 254
- 23.4 BMC Reset Control 255
- 23.5 System Initialization 255
- 24.1.2 Boot Control Support 257
- 24.1.3 Post Code Display 257
- 24.2.1 Power LED 257
- 24.2.2 System Status LED 257
- 24.1.1 BSP Identification 257
- 24.2.3 Chassis ID LED 259
- 24.3 Private Management I 260
- C Buses 260
- 24.4 Watchdog Timer 260
- 24.6 System Event Log (SEL) 261
- 24.7.2 Initialization Agent 262
- 24.8.2 BMC FRU ID Mapping 262
- 24.9.1 Signal Generation 263
- 24.10 Sensor Rearm Behavior 264
- 24.11 Processor Sensors 264
- 24.11.1.1 Processor Presence 265
- 24.12 Voltage Monitoring 266
- 24.13.1 Hot Swap Fans 267
- 24.13.3 Fan Domains 268
- 24.13.4 Nominal Fan Speed 268
- 24.13.4.1.2 Domain Maximum 269
- 24.13.4.2 Clamp 270
- 24.13.4.3 Sensor Failure 271
- 24.13.5.1 Fan Profiles 271
- 24.13.5.2 ASHRAE Compliance 272
- 24.18 Power Throttle Sensor 273
- 24.20.1 Semaphore Operation 274
- 24.21 HeartBeat LED 276
- 24.22 CSS LED 277
- 24.23 Global Fan Fault LED 277
- 24.25 Power Unit Management 278
- 24.25.1.1 Power Off 279
- 24.25.1.2 AC Lost 279
- 24.25.1.4 Power Unit Failure 279
- IPMI Sensor Characteristics 280
- Event Logging 281
- 24.29 BMC Self Test 282
- 24.30 BMC Test Commands 282
- 24.32 Hot-Swap Controller 284
- 24.34 CATERR Reporting 284
- 25.3 Sessions 287
- 25.4 Media Bridging 288
- 25.6.2 Receive Message Queue 289
- 25.6.5 SMM Interface 290
- 25.7.1 BMC as I 290
- C Master Controller on IPMB 290
- 25.7.2 IPMB LUN Routing 291
- 25.8.1 COM Port Switching 292
- 25.8.2 Terminal Mode 292
- 25.9 LAN Interface 293
- 25.9.3 RMCP / ASF Messaging 294
- 25.9.6 DHCP BMC Hostname 295
- 26. BMC Flash Update 299
- 26.3 Boot Recovery Mode 300
- 27. BIOS-BMC Interactions 302
- 28. BMC-HSC Interactions 303
- 29. Sensors 304
- Table 202. IBMC Core Sensors 306
- Contrib. To 307
- 30.1.1 I2C Interfaces 313
- 30.1.3 GPIO Pins 313
- 31.1 Platform Determination 314
- 31.2 System Initialization 314
- 31.3 System Event Log (SEL) 315
- 31.6 Temperature Monitoring 315
- 31.7 Disk Management 316
- 32.1 LUNs 317
- 32.2 Sensors 317
- 33. HSC Firmware Update 319
- Glossary 320
- Reference Documents 322
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